The present invention relates to an output buffer circuit for a high-speed semiconductor logic device such as a semiconductor memory and a microprocessor and, more particularly to an output buffer circuit for generating output data in response to a signal representing that input data will be supplied thereto after a predetermined time has passed.
FIG. 1 is a conventional output buffer circuit for a semiconductor memory. This output buffer circuit has a data input terminal IN connected to output terminals of a plurality of memory cells (not shown) through a bit line, a control terminal .phi. which receives a signal for disabling a data output, load and drive transistors 10 and 12, and a driver 14 for controlling the conduction states of the transistors 10 and 12 in accordance with a logic value of data supplied through the terminal IN. The driver 14 is operated to render the transistors 10 and 12 nonconductive while the disable signal is supplied from the terminal .phi.. A data output terminal OUT of the output buffer circuit is connected through a current path of the transistor 10 to a power source terminal VD to which a voltage VDD (e.g., 5 V) is supplied and which is grounded through a current path of the transistor 12. A capacitor 16 used as a load is connected to the data output terminal OUT. The capacitor 16 has a large capacitance.
Assume that data of logic values "1" and "0" are respectively stored in the first and second memory cells to be selectively accessed in response to an address signal. In this case, as shown in FIG. 2(A), when the address signal is changed to cause data of "1" to be read out from the first memory cell, the data of logic value "1" will be supplied from the first memory cell to the output buffer circuit after a predetermined period of time has passed. Then the transistors 10 and 12 are rendered conductive and nonconductive, respectively, in accordance with the data of logic value "1" to permit a charge current to flow into the capacitor 16. This causes the voltage of the data output terminal OUT to be increased to the VDD level, as shown in FIG. 2(B). Assume next that the address signal is changed to read out the data of "0" from the second memory cell. When the data of logic value "0" is supplied from the second memory cell to the output buffer circuit after a predetermined period of time, the transistors 10 and 12 are respectively rendered nonconductive and conductive. Therefore, a discharge current flows from the capacitor 16, so that the voltage of the data output terminal OUT is decreased to the ground potential level, as shown in FIG. 2(B).
When the charge and discharge currents with respect to the capacitor 16 are small, it takes a long time to change a voltage of the data output terminal OUT. In addition, since the capacitor 16 has a large capacitance, this time interval is mostly occupied by a memory access time TD which starts when the address signal is changed and terminates when a voltage of the capacitor 16 is changed to a level near the VDD or ground level. Therefore, the time TD impairs high-speed readout operation of the memory. The transistors 10 and 12 might have a large driving capacity for increasing the charge and discharge currents. However, this leads to an increase in power consumption.